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ADuM7510
APPLICATIONS INFORMATION
PRINTED CIRCUIT BOARD (PCB) LAYOUT
The ADuM7510 digital isolator requires no external interface
circuitry for the logic interfaces. Power supply bypassing is strongly
recommended at the input and output supply pins (see Figure 9).
Bypass capacitors are most conveniently connected between Pin 1
and Pin 2 for V DD1 and between Pin 15 and Pin 16 for V DD2 . The
capacitor value should be between 0.01 μF and 0.1 μF. The total
lead length between both ends of the capacitor and the input
power supply pin should not exceed 10 mm. Bypassing between
Pin 1 and Pin 8 and between Pin 9 and Pin 16 should also be
considered unless the ground pair on each package side is
connected close to the package.
Data Sheet
If the decoder receives no pulses for more than about 5 μs, the
input side is assumed to be unpowered or nonfunctional, in which
case, the isolator output is forced to a default low state by the
watchdog timer circuit (see Table 8).
The limitation on the magnetic field immunity of the device is
set by the condition in which induced voltage in the transformer
receiving coil is sufficiently large to either falsely set or reset the
decoder. The following analysis defines such conditions. The
ADuM7510 is examined in a 4.5 V operating condition because it
represents the most susceptible mode of operation of this product.
The pulses at the transformer output have an amplitude greater
than 1.5 V. The decoder has a sensing threshold of about 1.0 V,
V DD1
GND 1
V IA
V DD2
GND 2
V OA
thereby establishing a 0.5 V margin in which induced voltages
can be tolerated. The voltage induced across the receiving coil is
V IB
V IC
V ID
V IE
GND 1
ADuM7510
V OB
V OC
V OD
V OE
GND 2
given by
V = (? dβ / dt )∑∏ r n 2 ; n = 1, 2, …, N
where:
Figure 9. Recommended PCB Layout
See the AN-1109 Application Note for board layout guidelines.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the length of
time it takes for a logic signal to propagate through a component.
The propagation delay to a logic low output can differ from the
propagation delay to a logic high output.
β is the magnetic flux density.
r n is the radius of the n th turn in the receiving coil.
N is the number of turns in the receiving coil.
Given the geometry of the receiving coil in the ADuM7510 and
an imposed requirement that the induced voltage be, at most,
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated, as shown in Figure 11.
1000
INPUT (V Ix )
t PLH
t PHL
50%
100
OUTPUT (V Ox )
50%
Figure 10. Propagation Delay Parameters
10
1
Pulse width distortion is the maximum difference between
these two propagation delay values and is an indication of how
accurately the input signal timing is preserved.
Channel-to-channel matching refers to the maximum amount
the propagation delay differs between channels within a single
0.1
0.01
ADuM7510 component.
0.001
1k
10k 100k 1M 10M
100M
Propagation delay skew refers to the maximum amount the
propagation delay differs among multiple ADuM7510 com-
ponents operated under the same conditions.
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input
cause narrow (~1 ns) pulses to be sent via the transformer to
the decoder. The decoder is bistable and is, therefore, either set
or reset by the pulses indicating input logic transitions. In the
absence of logic transitions at the input for more than ~1 μs,
MAGNETIC FIELD FREQUENCY (Hz)
Figure 11. Maximum Allowable External Magnetic Flux Density
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.5 kgauss induces
a voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
If such an event occurs with the worst-case polarity during a
transmitted pulse, it reduces the received pulse from >1.0 V to
0.75 V, still well above the 0.5 V sensing threshold of the
decoder.
a periodic set of refresh pulses indicative of the correct input
state are sent to ensure dc correctness at the output.
Rev. B | Page 8 of 12
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